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Block Diagram
SHDN
4
Shutdown
V IN
5
SW
1
Circuitry
FB
+ Over
Voltage
- Comp
1.15 x V REF
Thermal
Shutdown
R
FB 3
-
Error
Amp
+
+
Comp
R
Q
Driver
n
S
-
R
S
Ramp
Generator
Oscillator
Reference
Current Limit
Comparator
-
Soft-Start
+
+
Amp
-
0.05
2
GND
Figure 4. Block Diagram
V OUT = V REF ? 1 + ------ 1 - ?
Circuit Description
The FAN5331 is a pulse-width modulated (PWM) current-mode
boost converter. The FAN5331 improves the performance of bat-
tery powered equipment by signi?cantly minimizing the spectral
distribution of noise at the input caused by the switching action of
the regulator. In order to facilitate effective noise ?ltering, the
switching frequency was chosen to be high, 1.6MHz. An internal
soft start circuitry minimizes in-rush currents. The timing of the soft
start circuit was chosen to reach 95% of the nominal output voltage
within maximum 5mS following an enable command when V IN =
2.7V, V OUT = 15V, I LOAD = 35mA and C OUT (EFFECTIVE) = 3.2 μ F.
The device architecture is that of a current mode controller with
an internal sense resistor connected in series with the N-chan-
nel switch. The voltage at the feedback pin tracks the output
voltage at the cathode of the external Schottky diode (shown in
the test circuit). The error ampli?er ampli?es the difference
between the feedback voltage and the internal bandgap refer-
ence. The ampli?ed error voltage serves as a reference voltage
to the PWM comparator. The inverting input of the PWM com-
parator consists of the sum of two components: the ampli?ed
control signal received from the 50m ? current sense resistor
and the ramp generator voltage derived from the oscillator. The
oscillator sets the latch, and the latch turns on the FET switch.
Under normal operating conditions, the PWM comparator resets
the latch and turns off the FET, thus terminating the pulse.
Since the comparator input contains information about the out-
put voltage and the control loop is arranged to form a negative
feedback loop, the value of the peak inductor current will be
adjusted to maintain regulation.
Every time the latch is reset, the FET is turned off and the cur-
rent ?ow through the switch is terminated. The latch can be
FAN5331 Rev. 1.0.1
6
reset by other events as well. Over-current condition is moni-
tored by the current limit comparator which resets the latch and
turns off the switch instantaneously within each clock cycle.
Over-Voltage Protection
The voltage on the feedback pin is sensed by an OVP Compar-
ator. When the feedback voltage is 15% higher than the nominal
voltage, the OVP Comparator stops switching of the power tran-
sistor, thus preventing the output voltage from going higher.
Applications Information
Setting the Output Voltage
The internal reference is 1.23V (Typical). The output voltage is
divided by a resistor divider, R1 and R2 to the FB pin. The out-
put voltage is given by
R
? R 2 ?
According to this equation, and assuming desired output volt-
age of 15V, good choices for the feedback resistors are,
R 1 =150k ? and R 2 =13.4k ? .
Inductor Selection
The inductor parameters directly related to device performances
are saturation current and dc resistance. The FAN5331 oper-
ates with a typical inductor value of 10μH. The lower the dc
resistance, the higher the ef?ciency. Usually a trade-off between
inductor size, cost and overall ef?ciency is needed to make the
optimum choice.
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